Generally, in a memory array of a DRAM (dynamic random access memory), one memory cell MCij is arranged (connected) at the intersecting position of bit line BLj provided in each column and word line WLi provided in each row, as seen in FIG. 6. Each memory cell MCij comprises one n-type MOS transistor TRij and one capacitor Cij. Each word line WLi is connected to word line driving circuit WDi in each row and each bit line BLj is connected to sense amplifier SAj in each column.
The executing writing in memory cell MCij, word line driving circuit WDi turns on transistor TRij by driving or activating word line WLi to the potential of the H level, and simultaneous to this, sense amplifier SAj moves the potential of bit line BLj into H level (VDD) or L level (VSS) according to the write information ("1" or "0"). In this way, charge voltage of VDD or VSS is obtained in capacitor Cij. Thereafter, word line driving circuit WDi drops word line WLi to the L level (VSS) and turns off transistor TRij. As a result, charging voltage or charge of "1" (VDD) or "0" (VSS) is maintained as memory information in capacitor Cij.
When executing reading, sense amplifier SAj precharges bit line BLj to a fixed potential (generally VDD/2) beforehand, and word line driving circuit WDi turns on transistor TRij by driving or activating word line WLi to the H level. Consequently, bit line BLj and capacitor Cij are short circuited, and the potential on bit line BLj changes slightly from the precharged level according to the stored charge in capacitor Cij. By sense amplifier SAj detecting and amplifying the slight potential change on said bit line BLj, the memory information in memory cell MCij is identified.
In order to reliably turn on an n-type MOS transistor TRij of a memory cell MCij in this type of memory array, it is necessary to give consideration to the substrate bias effect and threshold voltage VTN and make the H level of word line WLi into potential VPP (normally VDD+2VTN) which is higher than the power source voltage VDD. The threshold voltage VTN of the n-type MOS transistor is about 0.8 V so in a 3.3-V operation type DRAM which will become the mainstream in the future, a drive voltage VPP of about 5.0 (3.3+2.times.0.8) becomes necessary.
Consequently, the self increasing system was conventionally used which increases power source voltage VDD individually to VPP by installing a bootstrap circuit in the word line driving circuit, but in recent years, the internal power source system is being used more, which feeds output voltage VPP of voltage pump circuit as the driving power source voltage to each word line driving circuit by installing a voltage pump circuit, which constantly generates drive voltage VPP at the peripheral part of the memory array.
In FIG. 7, the configuration of a conventional word line driving circuit according to the internal power source system is shown. In this word line driving circuit, p-type MOS transistor 102 and n-type MOS transistor 104 comprises a word line driver 100 which is connected to the base terminal of each word line WLi. Namely, along with the drain terminal p-type MOS transistor 102 being connected to the base terminal of word line WLi, the drain terminal of n-type MOS transistor 104 is connected via n-type MOS transistor 116.
The source terminal of p-type MOS transistor 102 is connected to driving power source voltage terminal 106, and the gate terminal is connected to the output terminal of drive controlling circuit 108. The source terminal of n-type MOS transistor 102 is connected to ground terminal 110, and the gate terminal is connected to the output terminal of discharge controlling circuit 112. The input terminals of discharge controlling circuit 112 and drive controlling circuit 108 are connected to the output terminal of address decoder 114. Row address signal AX from address bus (not shown in the figure) is input into the input terminal of address decoder 114. Driving power source voltage VPP from voltage pump circuit (not shown in the figure) is being constantly fed to driving power source voltage terminal 106. Driving power source voltage VPP is also provided to drive controlling circuit 108. n-type MOS transistor 116 is a circuit for hot electron prevention as will be discussed later, power source voltage VDD is provided to the gate terminal, and is always in the on state.
When word line WLi is in the inactive (standby) state, the output voltage of drive controlling circuit 108 is the H level (VPP), p-type MOS transistor 102 is in the off state, the output voltage of discharge control circuit 112 is the H level (VDD), and n-type MOS transistor 104 is in the on state.
When driving word line WLi in order to write or read, along with the output voltage of drive controlling circuit 108 becoming the L level (VSS) in response to the output signal from address decoder 114, the output voltage of discharge controlling circuit 112 becomes the L level (VSS). In this way, along with p-type MOS transistor 102 taking on the on state, n-type MOS transistor 104 takes on the off state, electric current flows into word line WLi from driving power source voltage terminal 106 through p-type MOS transistor 102, and the potential of word line WLi is raised to VPP.
If writing or reading ends, along with the output voltage of drive controlling circuit 108 becoming the H level (VPP), the output voltage of discharge controlling circuit 112 becomes H level (VDD) in order to return word line WLi into the inactive state. In this way, along with p-type MOS transistor 102 taking on the off state, n-type MOS transistor 104 takes on the on state, and the charge on word line WLi flows into the ground terminal 110 side through n-type MOS transistors 116 and 104. As a result, the potential on word line WLi returns to L level (VSS) again.
When discharging word line WLi and returning to the inactive state (L level) after driving word line WLi as noted above, there is a fear of hot electrons being generated and the characteristics of n-type MOS transistor 104 deteriorating due to voltage of VPP being applied to n-type MOS transistor 104 and large electric current with a strong electric field flowing between the gate and source when n-type MOS transistor 116 is not provided. Therefore, the voltage applied to n-type MOS transistor 104 is suppressed to be low by inserting n-type MOS transistor 116 that is always turned on and is generating a drop in voltage.
However, the pitch of the word line becomes narrower as integration of the DRAM increases; thus, it is not possible to avoid the area of word line drive circuit 100 from becoming small. Therefore, the installation of n-type MOS transistor 116 for hot electron prevention in each word line driver 100 becomes very difficult in the layout of the circuit design.
Furthermore, in the conventional word line driving circuit, all the charge on word line WLi flows into ground terminal 10 energetically through n-type MOS transistor 104 during the discharge of word line WLi, but there is a tendency for the charge or electric current which flowed into said ground terminal 10 energetically to flow into adjacent word lines WLi-1 and WLi+1 as so-called ground noise through n-type MOS transistor 104 which is in the on state in the adjacent word line driver 100; thus, there was a fear of causing erroneous operation.
It is an object of the present invention to provide a word line driving circuit which accommodates for the narrowing pitch of the word lines with margin by making the layout area of the word line driver small along with eliminating the fear of creating ground noise.